Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design

The Fast Fourier Transform (FFT) has been one of the most popular and widely-used transform functions in communication hardware designs. With growing digital convergence, a single device needs to support multiple communication protocols, all of which need FFT computations. Currently, most FFT designs are either not shareable across applications or only among a fixed set of applications. This work proposes a novel reconfigurable FFT design called Spatio-Temporally-shAred Reconfigurable Fast Fourier Transform (STARFFT), which leverages on the partial dynamic reconfiguration technology such that it can be shared across arbitrary set of applications. STARFFT has a software driver that checks feasibility, schedules applications, and reconfigures the hardware. STARFFT hardware has several radix-2 pipelines that are time-multiplexed among applications such that significant reductions in hardware resource requirements and in power consumption are achieved. Experimental results show that STARFFT can reduce the total hardware resource usage by nearly 88% and the power consumption requirements by about 90%.