Hardware implementation of LU decomposition using dataflow architecture on FPGA

Author

Eljammaly, Mahmoud ; Hanafy, Yasser ; Wahdan, Ahmed ; Bayoumi, A.

Author_Institution

Arab Acad. for Sci. & Technol. & Maritime Transp., Cairo, Egypt

fYear

2013

fDate

27-28 March 2013

Firstpage

298

Lastpage

302

Abstract

Recent FPGA technology advances permitted the hardware implementation of selected software functions to enhance programs performance. Most of the work done was only concerned with integer operations. Little effort addressed floating point operations. In this paper we propose a dataflow implementation of the LU decomposition on FPGA. A modified Kernighan-Lin based task partitioning and assignment algorithm is presented in this paper. The algorithm showed acceptable improvement over existing techniques.

Keywords

field programmable gate arrays; mathematics computing; matrix decomposition; parallel processing; FPGA technology; Kernighan-Lin based task assignment algorithm; Kernighan-Lin based task partitioning algorithm; LU decomposition; dataflow architecture; field programmable gate array; lower-upper decomposition; lower-upper factorization algorithm; software function; software program performance; Field programmable gate arrays; Matrices; Multiprocessor interconnection; Parallel processing; Partitioning algorithms; Sparse matrices; FPGA; Kernighan-Lin algorithm; LU factorization; parallel processing; tagged-token dataflow architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Information Technology (CSIT), 2013 5th International Conference on

Conference_Location

Amman

Type

conf

DOI

10.1109/CSIT.2013.6588795

Filename

6588795