A Self-Calibrating Sub-Picosecond Resolution Digital-to-Time Converter

Author

Nagaraj, Geetha ; Miller, Scott ; Stengel, Bob ; Cafaro, G. ; Gradishar, T. ; Olson, Scott ; Hekmann, Ralf

Author_Institution

Motorola Labs., Plantation

fYear

2007

fDate

3-8 June 2007

Firstpage

2201

Lastpage

2204

Abstract

A novel self-calibrating high-resolution digital-to-time converter (DTC) achieves 1024 individual phase states with a resolution of 0.5 ps. The phase interpolation is done in steps, by using a cascade of coarse active delay locked line and a passive programmable fine delay. The DTC is capable of self-calibration by using an integrated dual mixer time domain (DMTD) circuit to overcome device mismatch and process variations. The DTC is constructed using 90 nm standard digital CMOS technology at 1 GHz RF frequency. Future improvements are expected to increase the resolution to 0.1 ps and below.

Keywords

CMOS digital integrated circuits; calibration; delay lock loops; digital-analogue conversion; active delay locked line; digital CMOS technology; frequency 1 GHz; integrated dual mixer time domain circuit; passive programmable fine delay; phase interpolation; self-calibrating digital-to-time converter; size 90 nm; sub-picosecond resolution digital-to-time converter; Active noise reduction; CMOS technology; Clocks; Delay effects; Delay lines; Frequency; Interpolation; Mixers; Phase locked loops; Signal resolution; RC delay line; delay locked loop; digital to time converter; dual mixer; time calibration;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium, 2007. IEEE/MTT-S International

Conference_Location

Honolulu, HI

ISSN

0149-645X

Print_ISBN

1-4244-0688-9

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2007.380397

Filename

4264309