• DocumentCode
    2975573
  • Title

    Numerical modeling of reduction in surface-related lags and current slump in GaAs FETs

  • Author

    Hafiz, Fadhlan ; Kumeno, M. ; Tanaka, T. ; Horio, K.

  • Author_Institution
    Fac. of Syst. Eng., Shibaura Inst. of Technol., Saitama, Japan
  • fYear
    2013
  • fDate
    22-25 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    We perform a two-dimensional transient analysis of field-plate GaAs MESFETs in which surface states are considered. Quasi-pulsed current-voltage curves are derived from the transient characteristics. It is shown that drain lag and current slump due to surface states are reduced by introducing a field plate because fixed potential at the field plate leads to reducing trapping effects by the surface states. Dependence of lag phenomena and current slump on field-plate length and SiO2 passivation layer thickness is also studied, indicating that the lags and current slump can be completely removed in some cases.
  • Keywords
    III-V semiconductors; Schottky gate field effect transistors; gallium arsenide; passivation; semiconductor device models; silicon compounds; surface states; transient analysis; GaAs; current slump; drain lag; field-plate gallium arsenide MESFET; field-plate length; gallium arsenide FET; lag phenomena; numerical modeling; quasipulsed current-voltage curves; silicon dioxide passivation layer thickness; surface state reduction; surface states; surface-related lags; transient characteristics; trapping effect reduction; two-dimensional transient analysis; Current slump; Gallium arsenide; Logic gates; MESFETs; Transient analysis; GaAs FET; current slump; drain lag; field plate; gate lag; surface state;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2013 - 2013 IEEE Region 10 Conference (31194)
  • Conference_Location
    Xi´an
  • ISSN
    2159-3442
  • Print_ISBN
    978-1-4799-2825-5
  • Type

    conf

  • DOI
    10.1109/TENCON.2013.6718452
  • Filename
    6718452