A simple architecture for ATM switching systems

Proposes a new self-routing ATM switch. The switch is constructed based on a banyan network in which each inter-stage link is dilated by the stage number power of 2, each dilated link is concentrated from 2 ^d+1 to 2^d multiple paths after stage d, and a new proposed shared-link design is used to reduce the cell blocking probabilities yielded by the concentration. By the scheme of interleaving the dilation, concentration, and sharing idle links after stage d, the new network has the advantages: (1) the delay-throughput performance is approximately the same as that of a knockout network with 2^d output links per output concentrator under the uniform traffic; (2) the hardware cost of network is of O(d2^dnlogn)≈O(nlogn) as d is small; (3) the self-routing mechanism is very simple and identical to that of a banyan network; and (4) it is very feasible in VLSI design that only three simple and regular CMOS chips are enough to construct any size of ATM switch