Title :
Tandem-crosspoint ATM: switch architecture and its cost-effective expansion
Author :
Oki, Eiji ; Yamanaka, Naoaki ; Yasukawa, Seisho
Author_Institution :
NTT Network Service Syst. Labs., Tokyo, Japan
Abstract :
This paper proposes a high-speed input and output buffering ATM switch, named the tandem-crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases
Keywords :
asynchronous transfer mode; buffer storage; multistage interconnection networks; HOL blocking; LSI; TDXP switch; cell reading algorithm; cost-effective expansion; head-of-line blocking; high-speed input/output buffering ATM switch; input buffer; internal line speed; output buffer; switch architecture; switch planes; tandem-crosspoint ATM; three-stage Clos switch configuration; throughput; Asynchronous transfer mode; CMOS technology; Costs; Electronic mail; Gallium arsenide; Hardware; Laboratories; Switches; Throughput; Very large scale integration;
Conference_Titel :
Broadband Switching Systems Proceedings, 1997. IEEE BSS '97., 1997 2nd IEEE International Workshop on
Conference_Location :
Taiwan
Print_ISBN :
0-7803-4443-X
DOI :
10.1109/BSS.1997.658893