Cost analysis of chip scale packaging

This paper documents a chip scale package (CSP) cost analysis using SEMATECH´s Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology