Power Optimization for Bus on Multimedia SoC

Reducing bus power consumption has become one of key issues for low power multimedia SoC design. The power which dissipated on interconnected bus includes the self transition power consumption and the coupled transition power consumption between every two signal lines. This paper, firstly propose an on-chip bus power consumption model. Then a heuristic algorithm is proposed to determine a physical order of signal lines in bus to minimize the power consumption on the interconnected bus. Experimental results show that the proposed heuristic algorithm is effective.