Implementation of PID architecture in FPGA for DC motor speed control

This paper deals with the hardware implementation of customized Proportional-Integral-Derivative (PID) architecture using FPGA for the speed control of permanent magnet DC motor. This architecture is embedded in FPGA using Verilog to implement speed control loop. Controller design, synthesis and analysis are completed by Xilinx ISE software and chipscope tool. Real time interface of this architecture with DC motor is demonstrated successfully, under dynamic load conditions. Re-configurability, high degree of parallelism, robustness of solution and DSP capability, these features of FPGA are explored to design the customized PID architecture. Further, closed loop system is simulated using MATLAB Simulink. Comparison of simulation results with the experimental results shows the efficacy of the proposed PID design.