Novel multilevel inverter with reduced number of switches and batteries

Design of an inverter has evolved from simple two leveled output to complex multi level output in the recent years. With the demand for high power inverter unit, multilevel inverters have been attracting extensive attention from academia as well as industry. Among the best-known topologies are the H-bridge cascade inverter, the capacitor clamping inverter and the diode clamping inverter. The significant advantages of multilevel configuration are voltage sharing both statical ly and dynamically and it produces better voltage waveforms with less harmonic contents. A conventional multilevel inverter requires `n´ DC sources to obtain 2n + 1 output voltage levels. One particular disadvantage is, it increases greater number of power semiconductor switches. This paper proposes a new concept of switching with reduced number of switches and batteries. This concept helps to reduce the complexity of switching compared to other conventional methods and DC Link counterparts. Proposed multilevel inverter having seven level output is experimentally validated with a simple resistive load.