• DocumentCode
    2977658
  • Title

    Fair Queuing Memory Systems

  • Author

    Nesbit, Kyle J. ; Aggarwal, Nidhi ; Laudon, James ; Smith, James E.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI
  • fYear
    2006
  • fDate
    9-13 Dec. 2006
  • Firstpage
    208
  • Lastpage
    222
  • Abstract
    We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fair queuing scheduling algorithms. The memory scheduler is fair and provides quality of service (QoS) while improving system performance. On a four processor CMP running workloads containing a mix of applications with a range of memory bandwidth demands, the proposed memory scheduler provides QoS to all of the threads in all of the workloads, improves system performance by an average of 14% (41% in the best case), and reduces the variance in the threads´ target memory bandwidth utilization from .2 to .0058
  • Keywords
    cache storage; microprocessor chips; multi-threading; processor scheduling; quality of service; shared memory systems; QoS; chip multiprocessor; memory bandwidth utilization; multithread memory scheduler; network fair queuing scheduling algorithm; quality of service; Art; Bandwidth; Delay; High performance computing; Interference; Processor scheduling; Quality of service; Scheduling algorithm; System performance; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Orlando, FL
  • ISSN
    1072-4451
  • Print_ISBN
    0-7695-2732-9
  • Type

    conf

  • DOI
    10.1109/MICRO.2006.24
  • Filename
    4041848