Energy-Aware Cache Partition Based on Way-Adaptable in CMP

Improving processor performance and reducing energy consumption of the cache has become research topic of the next-generation processor. This paper proposes a new mechanism that implemented in CMP to reduce energy consumption, which based on dynamically way-adaptable cache. The mechanism mainly consists of way reallocate module and dynamic power control module. Way reallocate module reassign ways between cores based on thread´s working set on the execution of the program. Our mechanism implements low power consumption by dynamic power control module. The proposed scheme based on dynamically way-adaptable cache is implemented and simulated. We applied several programs selected from SPEC2000 as benchmarks. Experiment results show our present scheme can reduce power consumption 18.6%, 14.7% on average with little performance degrade or no performance degrade.