• DocumentCode
    2977971
  • Title

    Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

  • Author

    Varadarajan, Keshavan ; Nandy, S.K. ; Sharda, Vishal ; Bharadwaj, Amrutur ; Iyer, Ravi ; Makineni, Srihari ; Newell, Donald

  • Author_Institution
    Indian Inst. of Sci., Bangalore
  • fYear
    2006
  • fDate
    Dec. 2006
  • Firstpage
    433
  • Lastpage
    442
  • Abstract
    CMPs enable simultaneous execution of multiple applications on the same platforms that share cache resources. Diversity in the cache access patterns of these simultaneously executing applications can potentially trigger inter-application interference, leading to cache pollution. Whereas a large cache can ameliorate this problem, the issues of larger power consumption with increasing cache size, amplified at sub-100nm technologies, makes this solution prohibitive. In this paper, in order to address the issues relating to power-aware performance of caches, we propose a caching structure that addresses the following: 1) Definition of application-specific cache partitions as an aggregation of caching units (molecules). The parameters of each molecule namely size, associativity and line size are chosen so that the power consumed by it and access time are optimal for the given technology. 2) Application-specific resizing of cache partitions with variable and adaptive associativity per cache line, way size and variable line size. 3) A replacement policy that is transparent to the partition in terms of size, heterogeneity in associativity and line size. Through simulation studies we establish the superiority of molecular cache (caches built as aggregations of molecules) that offers a 29% power advantage over that of an equivalently performing traditional cache
  • Keywords
    cache storage; microprocessor chips; multiprocessing systems; power aware computing; application-specific heterogeneous cache; chip multiprocessor; molecular cache; power-aware performance; replacement policy; Art; Costs; Delay; Energy consumption; Interference; Moore´s Law; Multicore processing; Pollution; Sun; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Orlando, FL
  • ISSN
    1072-4451
  • Print_ISBN
    0-7695-2732-9
  • Type

    conf

  • DOI
    10.1109/MICRO.2006.38
  • Filename
    4041866