A coefficient segmentation algorithm for low power implementation of FIR filters

The authors present a multiplication algorithm for the low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual coefficients into two primitive sub-components. The decomposition, performed using a heuristic approach, divides a given coefficient such that a part is produced which can be implemented using a single shift operation leaving another part with a reduced wordlength to be applied to the coefficient input of the hardware multiplier. This results in a significant reduction in the amount of switched capacitance and consequently power consumption. The algorithm has been used with a number of practical FIR filter examples achieving up to 63% saving in power. Results are provided which illustrate the effect of the algorithm on the amount of switched capacitance for different size multipliers, The paper provides a description of the algorithm, the evaluation procedure used, and associated results including overheads due to shift operations