• DocumentCode
    2978267
  • Title

    The cost of limit-cycle elimination in IIR digital filters using multiplier blocks

  • Author

    Dempster, A.G.

  • Author_Institution
    Westminster Univ., London, UK
  • Volume
    4
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    2204
  • Abstract
    Multiplier blocks significantly reduce the cost of multiplication in digital filters, especially in structures that allow large numbers of products of a single multiplicand. Some such structures, the direct form and cascaded second-order sections, have previously been shown to be less costly than the wave structure. In this paper, the effects of eliminating zero-input limit-cycles (LC), hereinafter called simply “limit-cycles”, from these structures is examined. The direct form no longer competes with the wave structure, but the cascade structure is still found to be the most cost-efficient
  • Keywords
    IIR filters; cascade networks; digital filters; limit cycles; multiplying circuits; IIR digital filters; cascade structure; limit-cycle elimination; multiplier blocks; single multiplicand; zero-input limit-cycles; Added delay; Adders; Costs; Digital filters; Feedback; IIR filters; Limit-cycles; Noise reduction; Performance analysis; Propagation delay;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.612758
  • Filename
    612758