مرکز منطقه ای اطلاع رساني علوم و فناوري - IEEE/ACM International Conference on Computer Aided Design. IEEE/ACM Digest of Technical Papers (Cat. No.02CH37391)

Keywords :

Boolean functions; VLSI; analogue integrated circuits; automatic test pattern generation; circuit CAD; circuit layout CAD; circuit optimisation; design for testability; hardware-software codesign; high level synthesis; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; integrated circuit testing; integrated memory circuits; leakage currents; low-power electronics; molecular electronics; parameter estimation; reduced order systems; statistical analysis; system-on-chip; timing; ATPG Boolean engines; CAD computation; DFT techniques; IC CAD; RT level verification; SAT Boolean engines; SoC technology; VLSI manufacturability; analog/RF simulation; chip-level communication structures; circuit-level analog CAD; combinational synthesis; device modeling; dynamic voltage scheduling; embedded system architecture customization; formal hardware verification; formal validation/synthesis techniques; gate level verification; hardware/software codesign compilation; high level synthesis; inductance modeling; inductance modelling; interconnect optimization; logic synthesis; low level aware behavioral synthesis; low power optimization; low-power design; memory issues; model order reduction; molecular electronics; noise effects; optimization; routing; satisfiability checking; simulation technologies; statistical power estimation techniques; statistical timing estimation; substrate modeling; subthreshold leakage modeling/reduction techniques; switch level verification; system-level analog design; system-level performance modeling; system-level power modeling; testing; timing analysis; timing-driven placement; transistor level optimization;