Minimizing power across multiple technology and design levels

Approaches to achieve low power and high-speed VLSIs are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage current in a standby mode, boosted gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, V_DD-hopping and V_TH-hopping are promising, which are cooperative approaches between circuit and software. Power consumed in the interconnect system can be reduced by a cooperative approach between application and layout as in bus shuffling. Other low-power design approaches are also discussed.