DocumentCode :
2978517
Title :
Optimisation of low voltage Field Plate LDMOS transistors
Author :
Cortes, I. ; Morancho, Frederic ; Flores, D. ; Hidalgo, S. ; Rebollo, J.
Author_Institution :
LAAS-CNRS, Univ. de Toulouse, Toulouse
fYear :
2009
fDate :
11-13 Feb. 2009
Firstpage :
475
Lastpage :
478
Abstract :
An alternative 3D RESURF method applied in power MOSFETs consists on placing a thick trench oxide of together with a poly-silicon layer inside the trench oxide together with a poly-silicon layer inside the trench along the drift region. The metal-thick-oxide acts as a field-plate (FP), enhancing the 3D RESURF lateral depletion which allows increasing the N-drift doping concentration. The feasibility of applying the FP concept in lateral DMOS devices has been analyzed in this paper by means of 1D analytical formulation, and by extensive 2D and 3D TCAD simulations.
Keywords :
optimisation; power MOSFET; semiconductor doping; 3D RESURF method; N-drift doping concentration; TCAD simulations; drift region; low voltage field plate LDMOS transistors; metal-thick-oxide; optimisation; poly-silicon layer; power MOSFET; thick trench oxide; Analytical models; Degradation; Doping; Electron devices; Indium phosphide; Low voltage; MOSFETs; Optimization methods; Silicon; Uninterruptible power systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices, 2009. CDE 2009. Spanish Conference on
Conference_Location :
Santiago de Compostela
Print_ISBN :
978-1-4244-2838-0
Electronic_ISBN :
978-1-4244-2839-7
Type :
conf
DOI :
10.1109/SCED.2009.4800537
Filename :
4800537
Link To Document :
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