A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution

Author

Taehee Cho ; Young-Taek Lee ; Euncheol Kim ; Jinwook Lee ; Sunmi Choi ; Seungjae Lee ; Dong-Hwan Kim ; Wook-Kee Han ; Young-Ho Lim ; Jae-Duk Lee ; Jung-Dal Choi ; Kang-Deog Suh

Author_Institution

Samsung Electron., Kyunggi, South Korea

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

28

Lastpage

29

Abstract

A 1 Gb NAND flash memory with 2b per cell uses 0.15 /spl mu/m CMOS and achieves simultaneous operation of 4 independent banks with 1.6 GMB/s program throughput. Fusing enables changing to 512 Mb 1b-per-cell NAND flash memory. Wordline ramping minimizes noise and peak current. Disturb mechanisms and noise related V/sub TH/ distribution shifts are minimized to improve read margins.

Keywords

CMOS memory circuits; NAND circuits; flash memories; multivalued logic; 0.15 micron; 1 Gbit; 3.3 V; CMOS; disturb mechanisms; fusing; multi-level NAND flash memory; nonuniform threshold voltage distribution; peak current; program throughput; read margins; wordline ramping; Acceleration; Capacitance; Consumer electronics; Costs; Coupling circuits; Design optimization; Interference; Size control; Threshold voltage; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912417

Filename

912417