Author :
Pathak, B. ; Cabrera, A. ; Christensen, G. ; Darwish, A. ; Goldman, M. ; Haque, R. ; Jorgensen, J. ; Kajley, R. ; Ly, T. ; Marvin, F. ; Monasa, S. ; Nguyen, Q. ; Pierce, D. ; Sendrowski, A. ; Sharif, I. ; Shimoyoshi, H. ; Smidt, A. ; Sundaram, R. ; Taub,
Author_Institution :
Intel Corp., Folsom, CA, USA
Abstract :
A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns asynchronous page mode access and synchronous burst reads up to 100 MHz with zero wait state.
Keywords :
CMOS memory circuits; flash memories; memory architecture; 0.18 micron; 1.8 V; 100 MHz; 64 Mbit; CMOS; asynchronous page mode access; flexible read while write flash memory; multi-partition architecture; synchronous burst reads; zero wait state; Counting circuits; Delay; Differential amplifiers; Flash memory; Flexible printed circuits; Latches; Logic; Pulse amplifiers; Pulse circuits; Voltage control;
