• DocumentCode
    2979013
  • Title

    Evaluating the Impact of Fault Recovery on Superscalar Processor Performance

  • Author

    Sato, Toshinori ; Chiyonobu, Akihiro

  • Author_Institution
    Syst. LSI Res. Center, Kyushu Univ., Fukuoka
  • fYear
    2006
  • fDate
    Dec. 2006
  • Firstpage
    369
  • Lastpage
    370
  • Abstract
    Current semiconductor technologies have become susceptible to high-energy neutrons from space. Following the trends in smaller transistors, lower supply voltage, and higher clock frequency, current microprocessors are susceptible to soft errors, which constitute the vast majority of hardware failures. Based on these trends, it is expected that the quality with respect to reliability becomes important as well as performance for microprocessors. In light of this, a lot of fault-tolerance microarchitectures are recently proposed. These studies mainly focus on detecting transient faults, and hence almost every previous study evaluated processor performance in the absence of faults. This analysis only presents the performance impact of constraints introduced by fault detection mechanism. One of the reasons why this evaluation methodology is widely selected is that faults are expected to be rare enough that the overall performance is determined by fault-free behavior. However, evaluating recovery cost of fault tolerant execution is also important, because it is predicted that transient hardware faults occur more frequently as semiconductor technology is improved. Therefore, this paper focuses on recovery from faults
  • Keywords
    computer architecture; fault diagnosis; fault tolerance; instruction sets; performance evaluation; system recovery; fault recovery; fault-tolerance microarchitecture; hardware fault; superscalar processor performance; transient fault detection; Clocks; Fault detection; Fault tolerance; Frequency; Hardware; Microarchitecture; Microprocessors; Neutrons; Space technology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Dependable Computing, 2006. PRDC '06. 12th Pacific Rim International Symposium on
  • Conference_Location
    Riverside, CA
  • Print_ISBN
    0-7695-2724-8
  • Type

    conf

  • DOI
    10.1109/PRDC.2006.33
  • Filename
    4041923