Optimized design of a delay line based analog to digital converter for digital power management applications

The proliferation of mobile electronic equipment is driving the need for aggressive real-time power management techniques, beyond the incremental efficiency improvements in DC-DC switching converters. In dynamic voltage scaling (DVS) power managament technique, performance, i.e. the operating clock frequency is adjusted with the time-varying workload and the supply voltage is scaled down dynamically with the clock frequency to meet the specific performance requirements. A new class of Analog-to-Digital Converter (ADC) architecture is a challenging requirement in DVS power management implementation. This paper presents an optimized hardware design of a delay line based ADC to meet the requirements of DVS power management, under direct performance control over a wide range of clock frequency. A novel formulation of digital error value based on target clock frequency and the corresponding regulated output voltage is presented with optimum hardware. Support for process, voltage, temperature (PVT) variations is incorporated in the design framework.