DocumentCode
2979381
Title
Powerful and feasible processor interconnections with an evaluation of their communications capabilities
Author
Wang, Qian ; Ziavras, Sotirios G.
Author_Institution
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fYear
1999
fDate
1999
Firstpage
222
Lastpage
227
Abstract
Scalable networks with very good topological properties are often impossible to build because of their prohibitively high wiring complexity. Such a network is the generalized hypercube (GH). It supports full-connectivity of all its nodes in each dimension and is characterized by outstanding topological properties. We propose a new class of scalable interprocessor connections, namely HOWs (Highly-Overlapping Windows), capable of lower complexity than GHs and comparable performance. HOWs are obtained from GHs by removing edges to produce systems of lower wiring complexity. They contain numerous highly-overlapping GHs of smaller size. The classical GH belongs to this new class of interconnections. We demonstrate that 2-DHOWs perform much better than binary hypercubes for important communications patterns
Keywords
computational complexity; hypercube networks; Highly-Overlapping Windows; Scalable networks; communications capabilities; generalized hypercube; processor interconnections; wiring complexity; Broadcast technology; Computational Intelligence Society; Cost function; Emulation; Hypercubes; Scalability; Switches; Very large scale integration; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures, Algorithms, and Networks, 1999. (I-SPAN '99) Proceedings. Fourth InternationalSymposium on
Conference_Location
Perth/Fremantle, WA
ISSN
1087-4089
Print_ISBN
0-7695-0231-8
Type
conf
DOI
10.1109/ISPAN.1999.778943
Filename
778943
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