Analysis of charge injection and trapping in MOS capacitors formed on p-type silicon substrates

The changes due to charge injection in p-substrate (n-channel) MOS capacitors during accumulation and inversion biasing have been studied. The testing methods used in the study include time-dependent-dielectric-breakdown (constant-voltage-stressed I-t), time-zero-dielectric-breakdown (ramp-voltage-stressed I-V), quasistatic C- V, and high frequency C-V (1-MHz) tests. When device characteristics have been obtained in inversion (positive gate voltage), two different light intensities have been used to vary the number of photogenerated minority carriers (electrons) available to form the inversion layer. Explanations are offered for the differences between the electrical characteristics in the three testing regions: accumulation, inversion under low light, and inversion under high light