On matching properties of R-2R ladders in high performance digital-to-analog converters

In this paper the matching properties of R-2R ladders are scrutinized in high resolution digital-to-analog converters. The error sources are categorized into systematic and topologic types in which two dominant sources of each type are precisely discussed. A handful of design considerations and effective layout techniques are proposed to reduce the distortion due to mismatch errors. Both theoretical analysis and simulation results confirm that the error induced by mismatch effect can be comparable with the LSB of the high performance DAC and should be carefully considered for high resolution digital-to-analog converters in order to preserve the desired dynamic specifications. Systematic and topologic mismatch errors are simulated in HSPICE and IntelliSuite, respectively. Simulations are carried out by using the TSMC model of 0.35µm CMOS Technology.