A simple digital background gain error calibration technique for pipelined ADCs

This paper presents a simple digital background calibration technique to eliminate the gain errors of 1.5bit/stage pipelined analog-to-digital converters caused by finite DC gain of stage amplifiers. In this technique, the gain errors are extracted by creating a mismatch between stage sub-ADC threshold voltages in the “split ADC” architecture derived from [1] and [2]. The technique is tested on a prototype 12bit 1.5bit/stage pipelined ADC with maximum 50dB amplifier DC gain. MATLAB and Simulink environment simulations show 19dB SNDR and 45dB SFDR improvements after calibration technique is applied on the first four stages of the ADC, which were limited to 52dB and 55dB before calibration.