Title :
Reduction of Interconnect Loading in Sub-100nm Technology by 3D Stacked-FinCMOS
Author_Institution :
Hong Kong Univ. of Sci. & Technol., Hong Kong
Abstract :
The paper describes a stacked-FinCMOS technology to form high density 3D integrated circuits with local clusters. Circuit design with the described process can utilize the mature 2D design methodology and software with minimal modifications. Standard cells and other building blocks have been designed with the stacked-FinCMOS technology. Preliminary results show that the described process can effectively increase the circuit density, reduce the capacitive loading, and at the same time maintain a reasonable heat dissipation.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; 3D stacked-FinCMOS; capacitive loading; circuit density; high density 3D integrated circuits; interconnect loading reduction; reasonable heat dissipation; Doping; Fabrication; FinFETs; Integrated circuit interconnections; Integrated circuit technology; Inverters; Paper technology; Routing; Scanning electron microscopy; Three-dimensional integrated circuits;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450064
