Reducing short channel effects in dual gate SOI-MOSFETs with a drain dependent gate bias

In this paper we propose a new dual gate SOI-MOSFET in order to reduce short-channel effects (SCEs). In the proposed structure, the bias of the second gate which is near the drain is dependent on the drain voltage. To investigate transistor characteristics, a two-dimensional (2-D) analytical model for the surface potential variation along the channel is developed. A comparison between our structure and the single-gate (SG) SOI MOSFET demonstrates that short channel effects like, hot carriers effect and the drain induced barrier lowering (DIBL) are reduced considerably in the proposed structure.