Title :
Low-Voltage Limitations of Nano-Scale CMOS LSIs: Current Status and Future Trends
Author :
Itoh, Kiyoo ; Takemura, Riichiro
Author_Institution :
Central Res. Lab. Ltd., Tokyo
Abstract :
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce VT variations.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; MOSFET; SRAM chips; electric potential; large scale integration; low-power electronics; nanoelectronics; DRAM sense amplifiers; FD-SOI; MOSFET threshold voltage variation reduction; SRAM cells; high-k metal gates; logic gates; low-voltage limitations; nanoscale CMOS LSI; repair techniques; CMOS logic circuits; Flip-flops; High K dielectric materials; Large scale integration; Logic arrays; Logic circuits; MOSFETs; Random access memory; Read-write memory; Threshold voltage;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450067
