DocumentCode :
2980397
Title :
A new enhanced SPFD rewiring algorithm [logic IC layout]
Author :
Cong, Jason ; Lin, Joey Y. ; Long, Wangning
fYear :
2002
fDate :
10-14 Nov. 2002
Firstpage :
672
Lastpage :
678
Abstract :
This paper presents an in-depth study of the theory and algorithms for the SPFD-based (set of pairs of functions to be distinguished) rewiring, and explores the flexibility in the SPFD computation. Our contributions are in the following two areas: (1) We present a theorem and a related algorithm for more precise characterization of feasible SPFD-based rewiring. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of our new algorithm is 70% higher than SPFD-based local rewiring algorithms (SPFD-LR) and 18% higher than the recently developed SPFD-based global rewiring algorithm (SPFD-GR). (2) In order to achieve more rewiring ability on certain selected wires used in various optimizations, we study the impact of using different atomic SPFD pair assignment methods during the SPFD-based rewiring. We develop several heuristic atomic SPFD pair assignment methods for area or delay minimization and show that they lead to 10% more selected rewiring ability than the random (or arbitrary) assignment methods. When combining (1) and (2) together, we can achieve 38.1% higher general rewiring ability.
Keywords :
circuit optimisation; circuit simulation; combinational circuits; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; logic design; logic simulation; table lookup; LUT-based FPGA; SPFD computation flexibility; SPFD rewiring algorithms; SPFD-GR; area/delay minimization selected rewiring ability; combinational circuits; global rewiring algorithms; heuristic atomic SPFD pair assignment methods; local rewiring algorithms; random/arbitrary assignment methods; rewiring feasibility characterization; selected wire optimizations; set of pairs of functions to be distinguished rewiring; Algorithm design and analysis; Automatic test pattern generation; Computer science; Delay; Field programmable gate arrays; Logic; Minimization methods; Network synthesis; Optimization methods; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN :
1092-3152
Print_ISBN :
0-7803-7607-2
Type :
conf
DOI :
10.1109/ICCAD.2002.1167604
Filename :
1167604
Link To Document :
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