Constraint identification for timing verification

A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, though vital for correct circuit function, has not been extensively treated in the CAD literature. These algorithms have been incorporated into a full-custom timing verifier, NTV.<>