Title :
Constraint identification for timing verification
Author :
Grodstein, J.J. ; Pan, J. ; Grundmann, B. ; Gieseke, B. ; Yen, Y.T.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
A novel set of algorithms are presented to deduce timing constraints from a set of transistors. The algorithms are robust, extremely fast, and work well on a very wide variety of full-custom design styles. Furthermore, they include glitch-based timing checks: a novel class of constraints which, though vital for correct circuit function, has not been extensively treated in the CAD literature. These algorithms have been incorporated into a full-custom timing verifier, NTV.<>
Keywords :
logic CAD; logic testing; NTV; algorithms; constraint identification; full-custom design styles; glitch-based timing checks; timing verification; Algorithm design and analysis; Analytical models; Circuit simulation; Clocks; Costs; Design automation; Latches; Logic devices; Robustness; Timing;
Conference_Titel :
Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-2055-2
DOI :
10.1109/ICCAD.1990.129828
