A design and tool reuse methodology for rapid prototyping of application specific instruction set processors

This paper proposes a design method and a tool reuse scheme for the rapid prototyping of application-specific instruction-set processors (ASIPs). We propose a three-level hierarchical architecture abstraction method for top-down processor design. We also propose a reusable architecture description language (READ) and a family of retargetable simulators that allow top-down processor description and prototyping from instruction-set design to RTL implementation