A methodological approach to implement CSP on FPGA

CSP (constraint satisfaction problems) and SAT (satisfiability of propositional formulae) are both well-studied examples of the NP-complete family of problems, which are respectively solved by backtracking search algorithms and Davis-Putnam based algorithms. In recent papers, a new and promising approach has appeared for solving SAT by configuring a logic circuit that is dedicated to solving each problem instance on field programmable gate arrays (FPGAs). The main goal of this paper is to prove the feasibility of a new approach for CSP resolution and to show, in a prototypical study, how FPGA technology can be used to improve CSP resolution. For this, we use two polynomial reductions which encode any CSP in a SAT specification, in order to study the influence of the complexity encoding on the resulting CSP on an FPGA