Title :
A 76 mm/sup 2/ 8 Mb chain ferroelectric memory
Author :
Takashima, D. ; Takeuchi, Y. ; Miyakawa, T. ; Itoh, Y. ; Ogiwara, R. ; Kamoshida, M. ; Hoya, K. ; Doumae, S.M. ; Ozaki, T. ; Kanaya, H. ; Aoki, M. ; Yamakawa, K. ; Kunishima, I. ; Oowaki, Y.
Author_Institution :
Semicond. Co., Toshiba Corp., Yokohama, Japan
Abstract :
An 8 Mb chain FeRAM uses 0.25 /spl mu/m 2-metal CMOS technology. A one-pitch-shift cell realizes 5.2 /spl mu/m/sup 2/ cell area. A chain architecture with a hierarchical wordline scheme gives 76 mm/sup 2/ die. Random access time is 40 ns, and cycle time is 70 ns at 3.0 V.
Keywords :
CMOS memory circuits; ferroelectric storage; low-power electronics; memory architecture; 0.25 micron; 3.0 V; 8 Mbit; CMOS technology; chain architecture; ferroelectric memory; hierarchical wordline scheme; one-pitch-shift cell; CMOS technology; Capacitance; Capacitors; Consumer electronics; Electrodes; Ferroelectric films; Ferroelectric materials; Nonvolatile memory; Random access memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912536
