DocumentCode
2981103
Title
A 1 V 10.7 MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using doublesampling finite-gain-compensation technique
Author
Cheung, V.S.L. ; Luong, H.C. ; Ki, W.H.
Author_Institution
Hong Kong Univ. of Sci. & Technol., China
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
52
Lastpage
53
Abstract
A 1 V 10.7 MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator uses modified double-sampling finite-gain-compensation. In a standard 0.35 /spl mu/m CMOS process at 1 V supply, the modulator achieves 42.8 MHz effective sampling frequency with 42.3 dB peak SNDR while dissipating 12 mW in 1.3 mm/sup 2/ chip area.
Keywords
CMOS integrated circuits; operational amplifiers; sigma-delta modulation; signal sampling; switched networks; 0.35 micron; 1 V; 10.7 MHz; 12 mW; 42.8 MHz; CMOS process; chip area; double-sampling finite-gain-compensation technique; effective sampling frequency; peak SNDR; switched-opamp bandpass /spl Sigma//spl Delta/ modulator; Band pass filters; Capacitors; Chromium; Clocks; Computer hacking; Delta modulation; Frequency measurement; MOS devices; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912542
Filename
912542
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