DocumentCode
2981120
Title
A low-power reconfigurable analog-to-digital converter
Author
Gulati, K. ; Hae-Seung Lee
Author_Institution
MIT, Cambridge, MA, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
54
Lastpage
55
Abstract
A reconfigurable analog-to-digital converter digitizes signals over a 1 Hz-10 MHz bandwidth and 6 to 16 b resolution with adaptive power consumption. The converter achieves this by reconfiguring between pipeline and /spl Delta//spl Sigma/ architectures and adjusting circuit parameters and bias currents.
Keywords
low-power electronics; network parameters; pipeline processing; sigma-delta modulation; /spl Delta//spl Sigma/ architectures; 1 Hz to 10 MHz; 6 to 16 bit; adaptive power consumption; bias currents; circuit parameters; low-power electronics; pipeline architectures; reconfigurable analog-to-digital converter; resolution; Analog-digital conversion; Bandwidth; Capacitors; Clocks; Energy consumption; Phase locked loops; Pipelines; Signal resolution; Switches; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912543
Filename
912543
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