Title :
A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication
Author :
Tanahashi, T. ; Kurisu, M. ; Yamaguchi, H. ; Nedachi, T. ; Arai, M. ; Tomari, S. ; Matsuzaki, T. ; Nakamura, K. ; Fukaishi, M. ; Naramoto, S. ; Sato, T.
Author_Institution :
NEC Corp., Tokyo, Japan
Abstract :
A 20-data-channel transceiver with a control channel allows uncoded data transfer with 13 ns latency. A digital DLL with a ring-interpolator tracks phase with 20 ps resolution. A pre-emphasis driver enables 2 Gb/s transmission per channel over a 7 m cable at 1.5 V. The effective full-duplex bandwidth reaches 10 GB/s.
Keywords :
data communication; delay lock loops; driver circuits; transceivers; 1.5 V; 2 Gbit/s; 7 m; control channel; digital DLL; full-duplex bandwidth; inter-processor communication; latency; multichannel transceiver circuit; pre-emphasis driver; ring interpolator; uncoded data transfer; Circuits; Clocks; Delay; National electric code; Sampling methods; Shift registers; Signal generators; Timing; Transceivers; Transmitters;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912545
