Title :
5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking
Author :
Tamura, H. ; Kibune, M. ; Takahashi, Y. ; Doi, Y. ; Chiba, T. ; Higashi, H. ; Takauchi, H. ; Ishida, H. ; Gotoh, K.
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
A 6 ns-latency 12 mW 5 Gb/s bidirectional link for short-haul (<5 m) balanced lines uses an on-chip switched-capacitor hybrid with echo-canceling capability. The clock-recovery circuit, based on a phase interpolator, makes the link tolerant to a 100 ppm difference between the frequencies of the transmit and receive clocks.
Keywords :
clocks; echo suppression; switched capacitor networks; synchronisation; 12 mW; 5 Gbit/s; 5 m; 6 ns; balanced line; bidirectional link; clock recovery circuit; echo cancellation; latency; on-chip switched capacitor hybrid; phase interpolator; plesiochronous clocking; Clocks; Delay; MOS devices; Optical signal processing; Phase locked loops; Signal generators; Switches; Transmitters; Virtual colonoscopy; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912547
