DocumentCode
2981294
Title
An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5 Gb/s optical communication
Author
Larsson, P.
Author_Institution
Lucent Technol. Bell Labs., Holmdel, NJ, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
74
Lastpage
75
Abstract
A 2.5 Gb/s optical receiver clock-recovery circuit in 0.25 /spl mu/m CMOS features 4 mV sensitivity and offset cancellation to enable an integrated limiting amplifier. A linear phase detector using a half-rate clock relaxes speed requirements. An active on-chip loop filter capacitor gives <0.1 dB jitter peaking.
Keywords
CMOS digital integrated circuits; optical receivers; synchronisation; 0.25 micron; 2.5 Gbit/s; CMOS clock recovery circuit; active on-chip loop filter capacitor; demux; half-rate clock; jitter; limiting amplifier; linear phase detector; offset cancellation; optical communication; optical receiver; sensitivity; Active filters; Capacitors; Circuits; Clocks; Detectors; Optical amplifiers; Optical filters; Optical receivers; Phase detection; Semiconductor optical amplifiers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912552
Filename
912552
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