A Low-Voltage Charge Pump Circuit with High Pumping Efficiency in Standard CMOS Logic Process

A new charge pump circuit feasible for the implementation with standard CMOS logic process is proposed. The proposed charge pump employs complementary dual charge-transfer paths and a simple two-phase clock. The charge transfer switches in each pumping stage can completely transfer the charges from the present stage to the next stage without suffering threshold voltage drop. Thus, the power efficiency is higher than that of the traditional schemes. The output voltage of charge pump circuit with eight stages is 8 V at 1.2 V power supply. The simulations demonstrate that the proposed charge pump exhibits a better pumping efficiency and a larger current drivability over the previous one.