VLSI Architecture for Low Power Turbo Decoder using Adaptive Sliding Window Algorithm

In this paper, a new decoding algorithm using adaptive sliding window is proposed. This new algorithm can detect and skip the calculation of convergent window metrics with same time of iterations. Experimental results show that this method slightly increases 4.7% of the hardware resource, but much reduces the backward metrics and log likelihood ratio calculation times. With a proper threshold value 6 at SNR 2.5 dB, 62.92% of Beta and LLR calculation can be suspended in comparison with traditional Turbo decoder in eight times of iterations. Finally, we have designed this decoder with TSMC 0.18 um 1P6M process in cell base design flow. When this chip operate at 77 MHz, throughput can reach 4.3 Mb/s, and whole chip size including IO PAD is 1.91x2.17 mm².