FPGA implementation of a FIR filter using residue arithmetic

Author

Loonawat, Gautam ; Siferd, Raymond E.

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

Volume

1

fYear

1996

fDate

20-23 May 1996

Firstpage

286

Abstract

Technological advances in VLSI have resulted in more dense and higher speed Field Programmable Gate Arrays (FPGAs), enabling them to be used in a variety of applications. Residue Arithmetic due to its inherent parallelism is ideally suited for implementing digital filters. This paper describes an efficient implementation of a fourth order Finite Impulse Response (FIR) filter combining the advantages of residue arithmetic and FPGAs. The coefficients and input data word width are 12 bits and the coefficients are fully programmable

Keywords

FIR filters; VLSI; digital filters; field programmable gate arrays; parallel architectures; residue number systems; 12 bit; FIR filter; FPGA implementation; VLSI; fourth order filter; inherent parallelism; input data word width; programmable coefficients; residue arithmetic; Adders; Digital arithmetic; Digital filters; Dynamic range; Field programmable gate arrays; Finite impulse response filter; Hardware; Multiprocessor interconnection networks; Programmable logic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1996. NAECON 1996., Proceedings of the IEEE 1996 National

Conference_Location

Dayton, OH

ISSN

0547-3578

Print_ISBN

0-7803-3306-3

Type

conf

DOI

10.1109/NAECON.1996.517659

Filename

517659