Title :
A quasi-floating point algorithm for combinational logic
Author :
Zhang, Xinggan ; Zhu, Zhaoda
Author_Institution :
Dept. of Electron. Eng., Nanjing Univ. of Aeronaut. & Astron., China
Abstract :
In this paper, a quasi-floating point algorithm is presented that is implemented with a combinational logic circuit for processing data at high speed in real-time. It is an approximate algorithm for computing module of a complex datum and nonlinear mapping of data. The circuit of quasi-floating point computing consists of normalizing unit, simple combinational logic computing unit and fixed-point restoring unit. If the remaining bit number N is 8, the relative error is less than 0.01
Keywords :
combinational circuits; floating point arithmetic; radar signal processing; real-time systems; approximate algorithm; bit number; combinational logic; fixed-point restoring unit; nonlinear mapping; normalizing unit; quasi-float point algorithm; relative error; Airborne radar; Artificial intelligence; Data engineering; EPROM; Electronic equipment; Equations; Hardware; Logic circuits; Transversal filters;
Conference_Titel :
Aerospace and Electronics Conference, 1996. NAECON 1996., Proceedings of the IEEE 1996 National
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-3306-3
DOI :
10.1109/NAECON.1996.517664
