Title :
A 128/spl times/128 CMOS imager with 4/spl times/128 bit-serial column-parallel PE array
Author :
Yamashita, H. ; Sodini, C.G.
Author_Institution :
Toshiba Corp., Yokohama, Japan
Abstract :
A 4/spl times/128 fine-grained bit-serial processing element array configured with four 1/spl times/128 SIMD processors is embedded in 128/spl times/128 pixel CMOS imager columns. The prototype imager chip performs /spl sim/220 operations/pixel at 20 MHz clock, which potentially affords pixel-rate color processing for a VGA format image.
Keywords :
CMOS image sensors; digital signal processing chips; image colour analysis; image processing equipment; interpolation; parallel architectures; reconfigurable architectures; 0.6 micron; 128 pixel; 16384 pixel; 20 MHz; CMOS imager; SIMD processors; Si; VGA format image; aperture correction; bit-serial column-parallel PE array; colour coding; colour interpolation; fine-grained processing element array; pixel-rate color processing; CMOS process; CMOS technology; Circuits; Color; Logic; Parallel processing; Pixel; Signal generators; Silicon; Streaming media;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912562
