A 8-bit 14OMS/s Pipelined ADC Using Folded Sample-and-Hold Stage

A 1.5-bit/stage 8-bit 140MS/s pipelined ADC with folded sampled-and-hold stage is presented. The proposed technique improves the nonlinearity without using complicated calibration circuitry and neither does it require extra calibration cycle. Only 17 comparators are required for a 5-bit flash ADC. This 8-bit pipelined ADC has been fabricated in a 0.18 um CMOS process. It dissipates 39 mW with a supply voltage of 1.8 V and occupies 0.71 mm² active area. The measured signal to noise plus distortion ratio (SNDR) is 46.4 dB at sampling rate of 140 MS/s. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.47-LSB and 0.86 -LSB, respectively.