Study and Design of mini-LVDS Receiver

According to mini-LVDS specification, the minimum setup and hold time of the receiver are analyzed. The design of a receiver basing on Chartered-Semiconductor 0.35 mum CMOS process is presented, and a simple simulation method is proposed, which can effectively evaluate performance of the receiver. The simulation results show that the setup and hold time of the receiver are all less than 0.8 ns. The circuit is implemented on the source drivers, and the testing results demonstrate that it can work at date rate of no less than 340 Mbps.