Title :
A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS
Author :
Choi, M. ; Abidi, A.A.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
Using array averaging and a wideband track-and-hold, a 6 b flash ADC achieves better than 5.5 effective bits for input frequencies to 600 MHz at 1 GSample/s, and 5 effective bits for 650 MHz input at 1.3 GSample/s. It consumes 500 mW from 3.3 V and occupies 0.8 mm/sup 2/ in 0.35 μm CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; 0.35 micron; 1 to 1.3 GHz; 3.3 V; 500 to 545 mW; 6 bit; 630 to 650 MHz; A/D converter; CMOS ADC; array averaging; flash ADC; wideband track/hold configuration; Circuits; Ethernet networks; FETs; Latches; Linearity; MOSFETs; Preamplifiers; Resistors; Signal resolution; Switches;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912571
