A 6 b 1.1 GSample/s CMOS A/D converter

Author

Geelen, G.

Author_Institution

Philips Semicond., Eindhoven, Netherlands

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

128

Lastpage

129

Abstract

High-speed ADCs are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6 b while the sampling rate (Fs) and effective resolution bandwidth (ERBW) requirements increase with each generation of storage system. Sample rates up to 800 MSample/s have been reported with ERBW=200 MHz. The ADC presented here achieves a maximum sample rate of 1.1 GSample/s and an EBBW of 450 MHz. This result is obtained with full flash interpolating/averaging architecture with distributed track-and-hold (T/H) in a standard 0.35 μm single-poly five-metal 3.3 V digital CMOS process. Chip area is 0.35 mm/sup 2/ and power consumption is 300 mW.

Keywords

CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; interpolation; 0.35 micron; 3.3 V; 300 mW; 450 MHz; 6 bit; CMOS A/D converter; CMOS flash ADC; distributed track/hold; effective resolution bandwidth; full flash interpolating/averaging architecture; high-speed ADCs; sampling rate; single-poly five-metal CMOS process; Bandwidth; CMOS technology; Circuits; Differential amplifiers; Interpolation; Parasitic capacitance; Resistors; Semiconductor device measurement; Signal generators; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912572

Filename

912572