DocumentCode
2981752
Title
A 14 b 40 MSample/s pipelined ADC with DFCA
Author
Yu, P.C. ; Shehata, S. ; Joharapurkar, A. ; Chugh, P. ; Bugeja, A.R. ; Xiaohong Du ; Sung-Ung Kwak ; Papantonopoulous, Y. ; Kuyel, T.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
136
Lastpage
137
Abstract
A DAC and feedback capacitor averaging (DFCA) technique used in a pipelined ADC achieves 84 dB SFDR and 74 dB SNR. Also external mismatch noise cancellation digitally improves the SNR. Excluding output drivers, the 0.6 μm double-poly BiCMOS ADC dissipates 860 mW from 3.3 V supply.
Keywords
BiCMOS integrated circuits; analogue-digital conversion; circuit feedback; integrated circuit noise; pipeline processing; 0.6 micron; 14 bit; 3.3 V; 74 dB; 860 mW; DAC/feedback capacitor averaging technique; SNR improvement; double-poly BiCMOS ADC; external mismatch noise cancellation; pipelined ADC; BiCMOS integrated circuits; Calibration; Circuit testing; Error correction; Hardware; Logic testing; Noise cancellation; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912576
Filename
912576
Link To Document