Title :
A 90 mW MPEG4 video codec LSI with the capability for core profile
Author :
Hashimoto, T. ; Kuromaru, S. ; Matsuo, M. ; Yasuo, K. ; Mori-iwa, T. ; Ishida, K. ; Kajita, S. ; Ohashi, M. ; Toujima, M. ; Nakamura, T. ; Hamada, M. ; Yonezawa, T. ; Kondo, T. ; Hashimoto, K. ; Sugisawa, Y. ; Otsuki, H. ; Arita, M. ; Nakajima, H. ; Fujim
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Fukuoka, Japan
Abstract :
A single-chip MPEG4 video codec LSI with 20 Mb embedded DRAM performs a QCIF 15 Hz H.263 codec, a Simple at L1 codec, and Core at L1 decoding. It consumes 90 mW at 54 MHz. This chip integrates a programmable DSP, 8 dedicated hardware engines, and interface units on a 75.68 mm/sup 2/ die using 0.18 /spl mu/m 1.8 V quad-metal CMOS technology.
Keywords :
CMOS digital integrated circuits; digital signal processing chips; large scale integration; video codecs; 0.18 micron; 1.8 V; 54 MHz; 90 mW; Core at L1 decoding; H.263 codec; MPEG4; Simple at L1 codec; core profile; dedicated hardware engines; embedded DRAM; interface units; programmable DSP; quad-metal CMOS technology; video codec LSI; Decoding; Digital signal processing chips; Energy consumption; Engines; Hardware; Large scale integration; MPEG 4 Standard; Pipelines; Shape; Video codecs;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912577
